The present invention relates to information storage of integrated circuit memory devices. More specifically, it relates to a temperature compensated resistor memory sensing circuit.
Integrated circuit (IC) memory devices have replaced magnetic-core memory devices due to their lower fabrication cost and higher performance. An IC memory circuit includes a repeated array of memory cells which store one state of a two state information (0 or 1), or multi-state information (for example, 00, 01, 10, or 11 of 4 states), together with support circuitries such as a row decoder, a column decoder, a write circuit to write to the memory cell array, a control circuitry to select the correct memory cell, and a sense amplifier to amplify the signal.
One early memory circuit is a flip-flop that has an output that is stable for only one of two possible voltage levels. The flip-flop maintains a given state for as long as there is power applied to the circuit, and changes state according to some external inputs. Typically, 6 transistors are used in each flip-flop. If the flip-flops are arranged in a circuit in such a way so that the information can be read from any memory cell at random, the circuit is called a SRAM (static random access memory) circuit. And a memory cell that can keep the stored information indefinitely as long as the circuit receives power is called a static memory cell.
The next generation memory cell is a DRAM (dynamic random access memory) cell. A DRAM cell typically consists of a transistor and a capacitor. The capacitor stores information in the form of electrical charge and the transistor provides access to the capacitor. Typically, a charge of one polarity stored in the capacitor represents a binary bit “1”, and the charge of the opposite polarity represents a binary bit “0”. In contrast to SRAM circuits, the DRAM circuits tend to lose information with time because of the inherent leakage of the capacitor charge, typically through substrate current in the memory circuits. To replenish the charge lost by the leakage, DRAM cells must be rewritten or refreshed at frequent intervals or else the information stored will be lost. A memory cell that requires refreshing at frequent interval is called a dynamic memory cell.
SRAM and DRAM memories cannot retain the stored information without a power source, therefore they belong to a class of memory called volatile memory. Another class of memory is called non-volatile memory which will still retain the stored information even after the power is turned off.
A typical non-volatile memory is ferroelectric random access memory (FRAM). Similar to a DRAM cell, a FRAM cell consists of an access transistor and a storage capacitor. The difference is that FRAM cell uses ferroelectric material for its capacitor dielectric. Ferroelectric material has high dielectric constant and can be polarized by an electric field. The polarization of the ferroelectric material remains until an opposite electrical field reverses it. The lifetime of the polarization of the ferroelectric material is typically about 10 years.
To read the information stored in the ferroelectric capacitor, an electric field is applied to the capacitor. There are more capacitor charges to move if this electric field reverses the cell into the opposite state than if the cell remains in the current state. This can be detected and amplified by a sense amplifier. Because of the possible reversal (or destroying) of the state of the ferroelectric capacitor after being read, the ferroelectric memory cell must be rewritten after a read, similar to a refresh of DRAM cells.
Recent developments of materials that have electrical resistance characteristics that can be changed by external influences have introduced a new kind of non-volatile memory, called RRAM (resistive random access memory). The basic component of a RRAM cell is a variable resistor. The variable resistor can be programmed to have high resistance or low resistance (in two-state memory circuits), or any intermediate resistance value (in multi-state memory circuits). The different resistance values of the RRAM cell represent the information stored in the RRAM circuit.
The advantages of RRAM are the simplicity of the circuit leading to smaller devices, the non-volatile characteristic of the resistor memory cell, and the stability of the memory state.
Since resistor is a passive component and cannot actively influence nearby electrical components, a basic RRAM cell can be just a variable resistor, arranged in a cross point resistor network to form a cross point memory array. To prevent cross talk or parasitic current path, a RRAM cell can further include a diode, and this combination is sometimes called a 1R1D (or 1D1R) cross point memory cell. To provide better access, a RRAM can include an access transistor, as in DRAM or FRAM cell, and this combination is sometimes called a 1R1T (or 1T1R) cross point memory cell.
The resistance state of a RRAM cell is referred to the storing (writing) or sensing (reading) methodology of the RRAM circuit. The term resistance state is related to the resistance value of the memory resistor (the resistance state can then be said to be the resistance of the memory resistor), but sensing the resistance value of the memory resistor often means sensing the voltage across the memory resistor (the resistance state can then be said to be the voltage across the memory resistor), or sensing the current through the memory resistor (the resistance state then can be said to be the current through the memory resistor).
The resistance states of the RRAM can be represented by different techniques such as structural state, polarization, or magnetization.
One example of structural state RRAM is a chalcogenide alloy. The term “chalcogen” refers to the elements in group VI of the periodic table. Chalcogenide alloys contain at least one of these elements such as the alloys of germanium, antimonium, or tellurium. Chalcogenide alloys can exhibit two different stable reversible structural states, namely an amorphous state with high electrical resistance and a polycrystalline state with lower electrical resistance. Since the binary information is represented by two different phases of the material, it is inherently non-volatile and requires no energy to keep the material in either of its two stable structural states. Resistive heating by an electrical current can be used to change the phase of the chalcogenide materials. The information can then be stored (or written) to a chalcogenide material by applying a current pulse to the chalcogenide material. A short pulse of high electrical current will give rise to a high temperature above the melting temperature to form the amorphous state, and a long pulse of lower electrical current will crystallize the material at a lower temperature to form the polycrystalline state. The information can then be sensed (or read) by sensing the voltage across the chalcogenide material using a constant current source, or by sensing the current through the chalcogenide material using a constant voltage source.
One example of polarization state is a polymer memory element. The resistance state of a polymer memory element is dependent upon the orientation of polarization of the polymer molecules. The polarization of a polymer memory element can be written by applying an electric field.
MRAM (magnetic random access memory) is another class of RRAM circuits using magnetic properties for storing information. Materials having perovskite structure such as magnetoresistive (MR) materials, giant magnetoresistive (GMR) materials, colossal magnetoresistive (CMR) materials, or high temperature superconductivity (HTSC) materials can store information by the magnetization state, and the information can be read or sensed by magnetoresistive sensing of such state. HTSC materials such as PbZrxTi1-xO3, YBCO (Yttrium Barium Copper Oxide, YBa2Cu3O7 and its variants), have their main use as a superconductor, but since their conductivity can be affected by an electrical current or a magnetic field, these HTSC materials can also be used as variable resistors in MRAM cells. The resistance of a magnetoresistive material can change depending on the direction of the magnetization vector and the direction of the sensing current (called anisotropic magnetoresistive response). The resistance change of magnetoresistance material can be significantly increased to a giant magnetoresistance effect by a super lattice ferromagnetic/non-ferromagnetic/ferromagnetic/anti-ferromagnetic layer. The magnetoresistance effect can also be increased with a spin dependent tunneling (SDT) junction. A basic SDT structure consists of two magnetic layers that are separated by a thin insulating film. The change in the magnetization in the two magnetic layers, relative to one another, results in a change in the tunneling current through the insulator. This gives a SDT magnetoresistance. Because the SDT uses tunneling current, the magnetoresistance is much higher than other magnetoresistive materials.
Recent studies on improvements of MRAM cells show that manganate perovskite materials of the Re1-xAexMnO3 structure (Re: rare earth elements, Ae: alkaline earth elements) such as Pr0.7Ca0.3MnO3 (PCMO), La0.7Ca0.3MnO3 (LCMO), Nd0.7Sr0.3MnO3 (NSMO) exhibit an abnormally large magnetoresistance (colossal magnetoresistance effect). ReMnO3 is an antiferromagnetic insulator, and the substitution of an Ae2+ ion to a Re3+ ion makes the change of Mn3+ to Mn4+ ionic valance. This results in ferromagnetic ordering and metallic conductivity.
From an electrical circuit point of view, the basic RRAM cell component is still a programmable resistor despite numerous material variations.
Numerous prior art disclosures have addressed the reading circuits of a RRAM cell to improve the reading speed, and to provide better stability against fabrication variations and time degradation. The basic reading scheme is to provide a constant current or a constant voltage to the memory resistor and to sense the corresponding response, e.g. sensing a voltage if a constant current is used, or sensing a current if a constant voltage is used. The corresponding response is then compared to a reference signal to determine the state of the memory resistor. A basic reading circuit using a constant current source is provided in FIG. 1. The constant current source 11 provides a constant current to the memory resistor 10 and generates a voltage Vmem 15 across the memory resistor 10. The voltage Vmem 15 is compared with a fixed reference voltage Vref 13 (generated by a reference voltage source 17) by a voltage comparator 12, and the output 16 of the voltage comparator 12 is then stored in the register 14. If Vmem is higher than Vref, a high voltage output is generated and a logic “1” is stored in register 14. If Vmem is lower than Vref, a low voltage output is generated and a logic “0” is stored in register 14. This basic reading circuit is a simplified schematic circuit. The practical circuit includes other circuit components such as a large memory cell array instead of just a memory resistor, a row decoder, a column decoder, a write circuit to write to the memory cell array, control circuitry to select the correct memory cell resistor, and a sense amplifier to amplify the signal before sending it to the voltage comparator. In this description, the logics “0” and “1” are assumed to correspond to a low voltage (ground potential) and a high voltage (power supply voltage).
Numerous improvements on the basic reading circuits have been disclosed. Brug et al, in U.S. Pat. No. 6,169,686, “Solid-state memory with magnetic storage cells” discloses a basic reading method of applying a read voltage Vrd to the selected memory resistor to generate a sense current to a current sense amplifier. The magnitude of the sense current indicates the resistance of the memory cell. Its continuation-in-part in Tran et al, U.S. Pat. No. 6,259,644, “Equipotential sense methods for resistive cross point memory cell arrays” discloses a method using other equal voltages applied to unselected word and bit lines to reduce the parasitic resistance in parallel or in series with the memory resistor.
Schlösser et al, in U.S. Pat. No. 6,462,979 “Integrated memory having memory cells with magnetoresistive storage effect” discloses read amplifier having a capacitor to compensate for any offset voltage at the control inputs of the operational read amplifier to allow data signal to be read comparatively reliably.
Numata et al, in U.S. Pat. No. 6,341,084 “Magnetic random access memory circuit” discloses a high precision and high speed reading of a magnetoresistive element by a charged capacitor to eliminate the possibility of breaking the magnetoresistive element due to excess voltage.
Perner et al. in U.S. Pat. No. 6,504,779, “Resistive cross point memory with on-chip sense amplifier calibration method and apparatus” discloses a RRAM circuit with a calibration controller to ensure that the sense amplifier perform reliably in view of process and geometry variations, and operating temperature and power supply voltage variations. The calibration controller of Perner is aimed at correcting the variations of the sense amplifier.
Perner et al. in U.S. Pat. No. 6,317,375, “Method and apparatus for reading memory cells of a resistive cross point array” discloses a RRAM circuit with a pull-up transistor to force the sense amplifier to a known and consistent condition to improve the reliability of the reading process.
Perner et al. in U.S. Pat. No. 6,262,625, “Operational amplifier with digital offset calibration” and in U.S. Pat. No. 6,188,615, “MRAM device including digital sense amplifier” discloses a direct injection change amplifier circuit which uses the charge time of a capacitor to determine the resistance of the memory cell.
To improve the reliability of the read circuit, numerous methods have also been disclosed with different reference cells.
Perner et al. in U.S. Pat. No. 6,185,143, “Magnetic random access memory (MRAM) device including differential sense amplifier” discloses a differential amplifier used to read the memory resistor. The differential amplifier has two inputs, one from the memory cell and the other from a reference cell. By comparing the two inputs, the differential amplifier generates an output response which is a binary state of the memory resistor. Perner discloses a column of reference cells to distinguish the value of the memory cells. The reference signal from Perner comes from a plurality of reference cells, each of similar construction as a memory cell.
Similarly, Moran et al., in U.S. Pat. No. 5,787,042, “Method and apparatus for reading out a programmable resistor memory” and in U.S. Pat. No. 5,883,827, “Method and apparatus for reading/writing data in a memory system including programmable resistors” discloses a differential amplifier with a reference resistor to read the memory resistor. The reference signal from Moran comes from a fixed resistor.
Tran et al., in U.S. Pat. No. 6,317,376, “Reference signal generation for magnetic random access memory devices” and in its division, U.S. Pat. No. 6,385,111, discloses reference circuits for MRAM devices. The reference circuit comprises 2 reference cells with different resistance states. By taking the average of the reference cells, Tran discloses a MRAM circuit that can tolerate variations in memory resistance due to manufacturing variations and other factors such as temperature gradients across the memory array, electromagnetic interference and aging. The reference signal from Tran also comes from a plurality of reference cells, each of similar construction as a memory cell.
Similarly, Lowrey et al, in U.S. Pat. No. 6,314,014, “Programmable resistance memory array with reference cells” discloses a plurality of reference cells to enhance the stability of the readability of the memory cells. The reference cells may be fabricated from the same material as the memory cells, the variations and drift in resistance values of the memory cells will be tracked and compensated for by the corresponding variations and drift in the reference cells. The reference signal from Lowrey also comes from a plurality of reference cells, each of similar construction as a memory cell.
Lowrey also discloses another method to generate a reference signal. The reference signal is developed by two programmable resistance elements, one programmed to the first resistance state and the other programmed to the second resistance state.
Many prior art RRAM cell reading schemes did not address the temperature dependence of the memory resistor and would be adequate if the memory resistor is temperature independent or if the temperature dependence of the memory resistor is relatively small. However, the memory resistor of a RRAM device can be strongly dependent on temperature. Shown in FIG. 2 is the resistance vs. temperature of a PCMO memory resistor. At high resistance state, the resistance of the PCMO memory resistor can vary from 150 kΩ at 30° C. to 1.5 kΩ at 120° C., a hundred times reduction in resistance (FIG. 2a). At low resistance state, the resistance of the PCMO memory resistor can vary from 12 kΩ at 0.1 V bias at 30° C. to 0.1 kΩ at 1V bias at 120° C. (FIG. 2b), more than a hundred times reduction in resistance. The resistance of the PCMO memory resistor can be bias voltage independent as in high resistance state (FIG. 2a), or can be bias voltage dependent, as in low resistance state (FIG. 2b), ranging from 1 kΩ at 1V bias to 12 kΩ at 0.1 V bias at 30° C. temperature.
The temperature dependence of the PCMO memory resistor creates an overlap in resistance state of the memory resistor from 1.5 kΩ to 12 kΩ. If the memory resistance falls into this range, without any additional information, the circuit could not determine if the resistance state is a high resistance state or a low resistance state. The prior art constant power source (constant current source or constant voltage source) scheme to read the resistance state of a memory resistor is not adequate because the constant power source did not contain any additional information to resolve the overlapping resistance range of the memory resistor.
FIG. 3 shows a sensing circuit using a constant current load nMOS transistor according to the scheme of FIG. 1. The transistor 30 is biased into a constant current transistor, therefore when the memory resistor 24 is at high resistance state, the voltage across the memory resistor will be high, and the voltage at 28 will be low, and when the memory resistor 24 is at low resistance state, the voltage at 28 will be high. The sensing voltage 28 will be inverted by the inverter 29 and outputs to a register (not shown).
The above sensing circuit comprises 3 sections, a memory resistor section 21 from a memory array, a control circuit 22 to control the reading of the information stored in the memory resistor, and a sensing amplifier 23 to read the information stored in the memory resistor and then store it in a register (not shown).
The memory resistor section 21 includes a memory resistor 24 with a diode 25. The diode 25 is optional. Its main purpose is to reduce or eliminate parasitic current. The polarity of the diode 25 is positioned so that the current runs through the memory resistor.
The sense amplifier 23 includes an inverter 29. The inverter 29 also acts as a voltage comparator with an internal reference voltage. The internal reference voltage is the toggle voltage of the inverter, typically about 0.5V. If the input Vin 28 to the inverter 29 is less than the toggle voltage, the output Vout 32 of the inverter 29 will be high to the power supply voltage. If the input Vin 28 to the inverter 29 is higher than the toggle voltage, the output Vout 32 of the inverter 29 will be low to the ground potential. The output response of the inverter is shown in the inset 20 of FIG. 3.
The control circuit 22 includes a constant current load nMOS transistor 30. During a read operation, a memory power supply voltage Vcc 26 is applied to the memory resistor 24, and a bias voltage VGC 27 is applied to the transistor 30. The transistor 30 is biased so that it performs as a constant current load nMOS transistor. If the drain voltage 28 is larger than the threshold voltage of the transistor 30, the current 31 flowing through the transistor 30 is a constant value. Also, the drain voltage 28 indicates how much the power supply voltage Vcc has dropped across the memory resistor 24.
If the constant current flows through a high resistance memory resistor, the voltage drop is high, thus the drain voltage 28 is low, and the inverter 29 will generate a high state output at the output 32. If the constant current flows through a low resistance memory resistor, the voltage drop is low, thus the drain voltage 28 is high, and the inverter 29 will generate a low state output.
Showing in FIG. 4 is the output response of the sensing circuit in FIG. 3. The output is the response of the transistor current 31 with respect to the transistor drain voltage 28. The voltage coordinate is the memory supply voltage normalized to 1 V. The output response curve consists of 2 segments, a linear segment 41 and a saturation segment 42. With a low drain voltage 28 (less than 0.2 V), the current 31 is essentially linear, and with a large drain voltage 28 (more than 0.2 V), the current 31 is essentially saturated to a constant value, about 35 μA as shown in FIG. 4. The constant current value of the output response curve depends on the bias voltage VGC 27. A large bias voltage 27 will shift the output response curve up (higher saturation current), and a small bias voltage 27 will shift the output response curve down (lower saturation current).
The various straight lines in FIG. 4 are the load lines for the memory resistor at different resistance states and operating temperatures (high resistance state at 30° C., 60° C., 80° C. and 100° C., low resistance state at 30° C. and 100° C.). The load lines all intersect the point (1V, 0A) because when the normalized drain voltage is at 1V, the drain voltage 28 is at the memory power supply Vcc, and therefore there is no current through the memory resistor, or the drain current 31 is zero. The slopes of the load lines are the conductance (inverse of the resistance) of the memory resistor at different operating temperatures and resistance states. These load lines are drawn for the PCMO material (shown in FIG. 2), therefore the resistance could depend on the bias voltage. The dependence of the high resistance state to the bias voltage is negligible. For low resistance state, the resistance is a function of the bias voltage, but for simplicity this dependence is not taken into account. Instead, the resistance at the operation point is chosen, such as 0.8 V at 30° C. at which the voltage across the memory resistor is 0.2 V, and a straight line is drawn to represent the 30° C. load line for the low resistance state.
The operation of the above sensing circuit for different temperatures is as followed. Since it is a constant current nMOS load at 30° C., the drain voltage 28 is 0.8 V for low resistance state. With the drain voltage higher than 0.5 V, the output 32 of the inverter 29 is 0 V, which is the ground potential for the memory circuit power supply voltage and represents a “0” state. At higher operating temperatures, the memory resistance at the low resistance state decreases. Therefore the drain voltage 28 increases with increased temperatures. The drain voltage 28 will still be higher than 0.5 V when the temperature increases, therefore there is no problem to sense the memory resistor at low resistance state at all temperature range.
The problem occurs at high resistance state. At low temperature, such as 30° C., the resistance of the high resistance state is very high (order of 100 kΩ). The constant current load nMOS transistor is biased at the linear region 41 as shown in FIG. 4 for the cases of 30° C. and 60° C. The drain voltage 28 in these cases is less than 0.2 V (less than the toggle voltage 0.5 V of the inverter) and therefore the output 32 of the inverter 29 is 1 V, which is the power supply voltage for the memory circuit and represents a “1” state. At higher operating temperature, 80° C. for example, the operating point of the constant current load nMOS transistor is in the saturation region and the load line in FIG. 4 shows a drain voltage of 0.65 V. This voltage is larger than the toggle voltage 0.5 V of the inverter 29; and as a result, the output 32 of the inverter 29 is at ground potential, representing a “0” state. Thus at high temperature, this circuit is not able to detect high resistance state signal.
To enable accurate high resistance state signal detection, the constant current load nMOS transistor can be biased at a higher constant current, such as 180 μA, as shown in FIG. 5. In FIG. 5, the load lines of the memory resistors are the same as in FIG. 4. The only difference is the response of the transistor current 31 with respect to the drain voltage 28. Higher bias voltage VGC results in a higher saturation current. This response is represented by a new output response curve with a linear region 46 and a saturation region 47. The saturation region 47 is biased at 180 μA so the sensing circuit is able to detect the high resistance state at a high temperature of 100° C. At 100° C., the high resistance state load line shows that the drain voltage 28 is 0.25 V, less than the toggle voltage, and therefore the inverter output will generate a high voltage, representing a “1” state. This bias scheme also works for the high temperature low resistance state of 100° C. However, it does not work at low temperature low resistance state. The load line for low resistance state at 30° C. shows a drain voltage 28 at less than 0.2 V, and the inverter will give a high “1” state.
Basically, this circuit can be biased to work at either low temperatures or high temperatures, but not both. Since the resistance of high resistance state at high temperatures overlaps with the resistance of low resistance state at low temperature, this circuit cannot resolve these resistance values and therefore cannot be operated in the entire temperature range.
In this description, the states 0 and 1 are assumed to correspond to a low voltage (ground potential) and a high voltage (power supply voltage). However, this is arbitrarily assigned and the opposite assignment would work equally well.
Shown in FIG. 6 is a complement constant current source pMOS sensing circuit. Similar to a constant current load nMOS sensing circuit, the constant current source pMOS bit sensing circuit comprises 3 sections: a memory resistor section 51 from a memory array, a control circuit 52 to control the reading of the information stored in the memory resistor, and a sensing amplifier 53 to read the information stored in the memory resistor and to store it in a register (not shown). The memory resistor section 51 includes a memory resistor 54 with a diode 55. The memory resistor circuit is connected to ground potential instead of connecting to the power supply voltage Vcc as in the case of the constant current load nMOS bit sensing circuit. The sense amplifier 53 is the same as in the case of the constant current load nMOS bit sensing circuit and comprises an inverter 59. The control circuit 52 includes a constant current source pMOS transistor 60 instead of an nMOS transistor as in the case of the constant current load nMOS bit sensing circuit. The operation of the constant current source pMOS bit sensing circuit is similar to that of the constant current load nMOS circuit. The basic difference is the selection of components (pMOS transistor vs. nMOS transistor), and therefore results in a different voltage bias scheme. Similar to the nMOS circuit, this pMOS circuit cannot be operated in the whole operating temperature range due to the overlapping of the resistance of the memory resistor in high resistance/high temperature and low resistance/low temperature states.
Shown in FIG. 7 is a constant current load nMOS transistor sensing circuit for a 1R1T RRAM. The basic difference is the presence of a transistor 65 instead of a diode. A transistor provides more access to the memory resistor at the cost of increasing circuit complexity. Operation of the 1R1T RRAM is similar to the 1R1D RRAM with the gate bias WL of the transistor 65 providing further isolation to the memory resistor, and therefore need to be turned on before accessing the memory resistor. A constant current source pMOS transistor sensing circuit for a 1R1T RRAM is similarly constructed by replacing the diode in FIG. 6 with a transistor. Again, these circuits cannot be operated in the whole operating temperature range due to the overlapping of the resistance of the memory resistor in high resistance/high temperature and low resistance/low temperature states.
Therefore it is advantageous to provide a simple reading circuit for RRAM so that the reading output is correct regardless of the operating temperatures.
It is advantageous to remove the overlapping states of the memory resistors due to variation in operating temperature to provide a reliable reading.
It is advantageous to resolve the various states of the memory resistors due to variation in operating temperature to provide a reliable reading.